1. Field of the Invention
The present invention relates to a read only memory, and in particular relates to a read only memory and operating method thereof.
2. Description of the Related Art
In chip design it is common to use low operating voltages to reduce energy consumption. However, for read only memories, operation in low voltages is difficult because of manufacturing weak bit cell. Operating speeds of read only memories are seriously affected when operating with low voltages. Thus, a new read only memory structure which can operate using low operating voltages with low power and high speeds is call for.
FIG. 1 is a 2×2 read only memory cell array. The 2×2 read only memory cell array includes a plurality of read only memory cells BC00, BC01, BC10 and BC11. The plurality of read only memory cells are respectively made up of a plurality of word lines WL[0] and WL[1], and a plurality of bit lines BL[0] and BL[1]. Each of the read only memory cells BC00, BC01, BC10 and BC11 includes an n-type transistor having a gate connected to a corresponding word line, a drain connected to a corresponding bit line and a source, and stores data according to the status of the source. For example, the gate of the n-type transistor in the read only memory cell BC00 is connected to a word line WL[0], the drain is connected to a bit line BL[0] and the source is floating so that a first data such as ‘0’ can be stored therein. The n-type transistor in the ROM cell BC01 is connected to the word line WL[0], the drain is connected to a bit line BL[1], and the source is connected to a low voltage level Vss so that a second data such as ‘1’ can be stored therein. The n-type transistor in the ROM cell BC10 is connected to a word line WL[1], the drain is connected to the bit line BL[0], and the source is floating so that the first data such as ‘0’ can be stored therein. The n-type transistor in the ROM cell BC11 is connected to the word line WL[1], the drain is connected to the bit line BL[1], and the source is connected to low voltage level Vss so that the second data such as ‘1’ can be stored therein. The reading procedure is described hereafter. For example, when the ROM cell BC00 is read, the word line WL[0] is selected so that the voltage potential at the source of the n-type transistor in the ROM cell BC00 is delivered to the bit line BL[0]. However, the n-type transistor of the ROM cell BC00 is floating so that the voltage potential at the bit line BL[0] is not affected. Hence, the content of the ROM cell BC00 is ‘0’. Also, when the ROM cell BC11 is read, the word line WL[0] is selected so that the voltage potential at the bit line BL[1] can be discharged by the n-type transistor of the ROM cell BC11. Hence, the data ‘1’ stored in the ROM cell BC11 can be determined by reading the bit line BL[1] according to the discharge statement.
Nevertheless, the discharge at the bit lines may be affected by low operating voltages. The FIG. 2 shows an example with a waveform graph, which describes signal status of the ROM cell BC11 of FIG. 1 when it operates at a low operating voltage. The signal Clk is a clock. There is a pre-charge time interval 202 at the time sequence of the bit line BL[1] signal. After the word line WL[1] is selected, the time sequence of the bit line BL[1] signal enters into a discharge time interval 204. However, a low operating voltage leads to a tiny discharge current at bit line BL[1] such that the bit line BL[1] signal can not discharge completely. Eventually, it is difficult for other circuits to correctly determine the stored data in the ROM cell BC11.